The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a semiconductor device with a buried gate and a method for fabricating the same.
As semiconductor devices such as DRAM shrink in size, it becomes more difficult to pattern a gate line and ensure a static capacitance (Cs). To solve the difficulty in patterning the gate line and ensuring the static capacitance (Cs), a buried gate structure has been intensively developed.
The buried gate structure has no problem in patterning the gate line and can ensure the static capacitance (Cs) because a parasitic capacitance between a gate line and a bit line is reduced.
FIG. 1 is a cross-sectional view of a conventional semiconductor device with a buried gate.
Referring to FIG. 1, an isolation layer 12 is formed in a semiconductor substrate 11, and a trench 15 having a certain depth is formed in the semiconductor substrate 11 by an etch process using a hard mask layer 14. A gate insulation layer 16 is formed on the surface of the trench 15. A buried gate 17 and 18 is formed on the gate insulation layer 16 to fill a portion of the trench 15. An interlayer insulation layer 19 is formed over the buried gate to fill the other portion of the trench 15. A junction region 13 is formed in the semiconductor substrate 11 on both sides of the trench 15.
To form the conventional buried gate illustrated in FIG. 1, a gate conductive layer is deposited until the trench is filled, and a chemical mechanical polishing (CMP) process and an etch-back process are sequentially performed.
According to the prior art, the gate conductive layer used as the buried gate is formed by stacking a titanium nitride (TiN) layer 17 and a tungsten (W) layer 18, instead of a polysilicon layer. Hence, the resistance of the buried gate is reduced.
However, since the titanium nitride (TiN) layer 17 has a high work function, an electric field increases in a cell structure of a DRAM implemented with NMOSFET. In particular, since the electric field further increases in the junction region 13 where a storage node contact hole and a bit line contact hole are met, a gate induced drain leakage (GIDL) characteristic is degraded.